I C - Serial data bus for communication integrated circuits using two bidirectional communication lines (SDA and SCL). Used to connect the low-speed peripheral components to the motherboard, embedded systems and mobile phones. 
I ² C uses two bi-directional lines, tightened to the supply voltage and managed through an open collector or open drain - Serial data line and serial line clock. Standard +5 V or +3.3 V, but allowed other. 
Classic includes addressing 7-bit address space with 16 reserved addresses. This means up to 112 addresses available for connecting peripherals on the same bus. 
Basic Operation - 100 kbit / sec (10 kbits / s in the mode with low speed). Note that the standard permits the suspension clock for slow devices. 
Exchange procedure begins with the fact that the master generates a START condition: generates a signal transition on the SDA line HIGH LOW state in at a high level on the line SCL. This transition is perceived by all devices connected to the bus, as a sign of the beginning of the exchange procedures. Clock generation - it is always the duty of the master; Each master generates its own synchronizing signal when transferring data on the bus. Exchange procedure is completed by the fact that the leading forms STOP state - state transition on the SDA line low in the HIGH state at a high state on SCL. START and STOP condition is always produced by the master. It is believed that the bus is busy after the START-latching. Bus is considered liberated some time after latching STOP. When sending parcels via I ² C each master generates its clock line SCL. After the formation of the state START, leading down to the state of the SCL line LOW and puts on SDA MSB of the first byte of the message. The number of bytes in the message is not limited. Specification I ² C bus allows changes on the SDA line only at a low level signal on SCL. These are valid and should remain stable only during the high state of sync. For an acknowledgment byte from the master-slave transmitter-receiver in the protocol specification exchange via I ² C introduce a special acknowledgment bit, exhibited on SDA bus after receiving 8 bits of data.